Altera Cyclone V Device Handbook page 232

CV-52007
2014.01.10
Programming EPCS Using the JTAG Interface
To program an EPCS device using the JTAG interface, connect the device as shown in the following figure.
Figure 7-8: Connection Setup for Programming the EPCS Using the JTAG Interface
EPCS Device
For more information, refer to
the MSEL pin settings.
Use the CLKUSR pin to supply
the external clock source to drive
DCLK during configuration.
Programming EPCQ Using the JTAG Interface
To program an EPCQ device using the JTAG interface, connect the device as shown in the following figure.
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
Send Feedback
V V V
CCPGM CCPGM CCPGM
10 kΩ 10 kΩ 10 kΩ
GND
DATA
DCLK
nCS
ASDI
Programming EPCS Using the JTAG Interface
V V
CCPD CCPD
FPGA Device
nSTATUS TCK
CONF_DONE
TDO
nCONFIG
nCE
TMS
TDI
AS_DATA1
DCLK
Serial
nCSO
Flash
ASDO
Loader
1 kΩ
MSEL[4..0]
CLKUSR
Instantiate SFL in your
GND
design to form a bridge
between the EPCS and the
10-pin header.
Connect the pull-up
resistors to V
3.0- or 3.3-V power supply.
The resistor value can vary
from 1 kΩ to 10 kΩ. Perform
signal integrity analysis to
select the resistor value for
your setup.
V
CCPD
Pin 1
Download Cable
GND
10-Pin Male Header
(JTAG Mode) (Top View)
7-17
at a
CCPGM
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