Modular I/O Banks For Cyclone V St Devices; I/O Element Structure In Cyclone V Devices; I/O Buffer And Registers In Cyclone V Devices - Altera Cyclone V Device Handbook

CV-52005
2014.01.10

Modular I/O Banks for Cyclone V ST Devices

Table 5-22: Modular I/O Banks for Cyclone V ST Devices
Note: The HPS row and column I/O counts are the number of HPS-specific I/O pins on the device. Each HPS-
specific pin may be mapped to several HPS I/Os.
FPGA I/O Bank
HPS Row I/O Bank
HPS Column I/O Bank
FPGA I/O Bank
Related Information
I/O Banks Locations in Cyclone V Devices
Guideline: Use the Same V
Provides guidelines about V

I/O Element Structure in Cyclone V Devices

The I/O elements (IOEs) in Cyclone V devices contain a bidirectional I/O buffer and I/O registers to support
a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.
The IOEs are located in I/O blocks around the periphery of the Cyclone V device.
The Cyclone V SE, SX, and ST devices also have I/O elements for the HPS.

I/O Buffer and Registers in Cyclone V Devices

I/O registers are composed of the input path for handling data from the pin to the core, the output path for
handling data from the core to the pin, and the output enable (
output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchro-
nization.
I/O Features in Cyclone V Devices
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Member Code
Package
3A
3B
4A
5A
5B
6A
6B
7A
7B
7C
7D
8A
Total
CCPD
CCPD
Modular I/O Banks for Cyclone V ST Devices
D5
F896
32
48
80
32
16
56
44
19
22
12
14
80
455
on page 5-19
for All I/O Banks in a Group
and I/O banks groups.
D6
F896
32
48
80
32
16
56
44
19
22
12
14
80
455
on page 5-17
) path for handling the
OE
5-27
signal to the
OE
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