Altera Cyclone V Device Handbook page 285

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PHY IP Embedded Reset Controller.........................................................................................................3-1
Embedded Reset Controller Signals..............................................................................................3-1
Power-Up.....................................................................................................................................3-3
Operation.....................................................................................................................................3-4
User-Coded Reset Controller.....................................................................................................................3-5
User-Coded Reset Controller Signals............................................................................................3-6
.......................................................................................................................................................3-7
Operation.....................................................................................................................................3-8
Configuration..............................................................................................................................3-9
Operation...................................................................................................................................3-10
Transceiver Reset Using Avalon Memory Map Registers....................................................................3-11
Clock Data Recovery Manual Lock Mode Reset Sequence..................................................................3-12
Control Settings for CDR Manual Lock Mode..........................................................................3-12
Resetting the Transceiver in CDR Manual Lock Mode............................................................3-13
Resetting the Transceiver During Dynamic Reconfiguration.............................................................3-13
is Required during Device Operation....................................................................................3-14
Transceiver Blocks Affected by the Reset and Powerdown Signals....................................................3-14
Transceiver Power-Down.........................................................................................................................3-15
Document Revision History.....................................................................................................................3-15
PCI Express...................................................................................................................................................4-2
PIPE Transceiver Datapath............................................................................................................4-3
PCIe Supported Features................................................................................................................4-4
PCIe Supported Configurations and Placement Guidelines......................................................4-7
Gigabit Ethernet.........................................................................................................................................4-11
Gigabit Ethernet Transceiver Datapath......................................................................................4-13
XAUI............................................................................................................................................................4-16
Transceiver Datapath in a XAUI Configuration.......................................................................4-17
XAUI Supported Features............................................................................................................4-19
Cyclone V Device Handbook Volume 2: Transceivers
TOC-3
Altera Corporation

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