I 2 C Controller Programming Model; Slave Mode Operation - Altera Cyclone V Device Handbook

cv_54020
2013.12.30
2
Table 20-4: HPS I
Signal Name
i2c_scl
i2c_out_clk
i2c_sda
i2c_out_data
Related Information
I/O Buffer Megafunction
For more information on configuring open drain I/O buffer to connect I
please refer to Altera I/O Buffer (ALTIOBUF) Megafunction User Guide
2
I C Controller Programming Model
This section describes the programming model for the I
operation modes. †
Note: Each I2C controller should be set to operate only as an I
simultaneously. Ensure that bit 6 (IC_SLAVE_DISABLE) and 0 (IC_MASTER_MODE) of the
IC_CON register are never set to 0 and 1, respectively. †

Slave Mode Operation

Initial Configuration
To use the I
1. Disable the I
2. Write to the IC_SAR register (bits 9:0) to set the slave address. This is the address to which the I
controller responds. †
Note:
3. Write to the IC_CON register to specify which type of addressing is supported (7- or 10-bit by setting
bit 3). Enable the I
and a 0 to bit 0 (MASTER_MODE). †
I2C Controller
Send Feedback
C Signals for FPGA Routing
Signal Width
1 bit
1 bit
1 bit
1 bit
2
C controller as a slave, perform the following steps: †
2
C controller by writing a 0 to bit 0 of the IC_ENABLE register. †
2
The reset value for the I
address, you can safely skip this step.
2
C controller in slave-only mode by writing a 0 into bit 6 (IC_SLAVE_DISABLE)
Direction
Input
Output
Input
Output
2
C controllers based on the two master and slave
C controller slave address is 0x55. If you are using 0x55 as the slave
2
I C Controller Programming Model
Description
Incoming I
source. This is the input
SCL signal
Outgoing I2C clock.
Open drain signal and
synchronous to HPS
peripheral clock
Incoming I
is the input SDA signal.
Outgoing I2C data.
Open drain signal and
synchronous to HPS
peripheral clock.
2
C signals to external I/O pins,
2 2
C master or as an I C slave, never both
20-13
2
C clock
2
C data. This
2
C
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