Cortex-A9 Mpu Subsystem Register Implementation - Altera Cyclone V Device Handbook

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Event Trace
Related Information
• CoreSight Debug and Trace
• ARM Infocenter (www.infocenter.arm.com)
Event Trace
Events from each processor can be used as inputs to the PTM. The PTM can use these events as trace and
trigger conditions.
For more information about the trigger and trace capabilities, refer to the CoreSight PTM-A9 Technical
Reference Manual, Revision r1p0, available on the ARM website (infocenter.arm.com).
Related Information
• Performance Monitoring Unit
• ARM Infocenter (www.infocenter.arm.com)
Cross-Triggering
The PTM can export trigger events and perform actions on trigger inputs. The cross-trigger signals interface
with other HPS debugging components including the FPGA fabric. Also, a breakpoint in one processor can
trigger a break in the other.
For detailed information about cross-triggering and about debugging hardware in the MPU, refer to the
CoreSight Debug and Trace chapter in the Cyclone V Device Handbook, Volume 3.
Related Information
CoreSight Debug and Trace

Cortex-A9 MPU Subsystem Register Implementation

The following configurations are available through registers in the Cortex-A9 subsystem:
• All processor-related controls, including the MMU and L1 caches, are controlled using the Coprocessor
15 (CP15) registers of each individual processor.
• All SCU registers, including control for the timers and GIC, are memory map accessible
• All L2 cache registers are memory-mapped.
For an address map of peripheral slave ports, including the SCU and L2 cache, refer to the Introduction to
the Hard Processor System chapter in the Cyclone V Device Handbook, Volume 3. For detailed definitions of
the registers for the Altera Cortex-A9 MPU subsystem, refer to the Cortex-A9 MPCore Technical Reference
Manual, and the CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, Revision r3p2,
available on the ARM website (infocenter.arm.com).
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
• ARM Infocenter (www.infocenter.arm.com)
Altera Corporation
on page 7-1
on page 6-11
on page 7-1
on page 1-1
Cortex-A9 Microprocessor Unit Subsystem
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2013.12.30
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