Altera Cyclone V Device Handbook page 85

4-28
Zero-Delay Buffer Mode
Figure 4-28: Example of Phase Relationship Between the PLL Clocks in Normal Compensation Mode
Zero-Delay Buffer Mode
In ZDB mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through
the device. This mode is supported on all Cyclone V PLLs.
When using this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee
clock alignment at the input and output pins. You cannot use differential I/O standards on the PLL clock
input or output pins.
To ensure phase alignment between the
instantiate a bidirectional I/O pin in the design. The bidirectional I/O pin serves as the feedback path
connecting the
ended I/O standard. The PLL uses this bidirectional I/O pin to mimic and compensate for the output delay
from the clock output port of the PLL to the external clock output pin.
Note: To avoid signal reflection when using ZDB mode, do not place board traces on the bidirectional I/O
pin.
Altera Corporation
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
Dedicated PLL
Clock Outputs
The external clock output
can lead or lag the PLL
internal clock signals.
and ports of the PLL. The bidirectional I/O pin must always be assigned a single-
fbout fbin
Phase Aligned
pin and the external clock output (
clk
) pin in ZDB mode,
CLKOUT
Clock Networks and PLLs in Cyclone V Devices
CV-52004
2014.01.10
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