Altera Cyclone V Device Handbook page 364

2-26
Quartus II Software-Selected Receiver Datapath Interface Clock
Figure 2-21: Receiver Datapath Interface Clocking for Non-Bonded Channels
Channel 1
Channel 0
The following figure shows the receiver datapath interface of three bonded channels clocked by the
tx_clkout[0] clock. The tx_clkout[0] clock is derived from the central clock divider of channel 1
or 4 of the two transceiver banks.
Figure 2-22: Receiver Datapath Interface Clocking for Three Bonded Channels
Channel 2
Channel 1
Channel 0
Altera Corporation
RX
Phase
Receiver Data
Compensation
FIFO
Parallel Clock (Recovered Clock)
RX
Phase
Receiver Data
Compensation
FIFO
Parallel Clock (Recovered Clock)
RX
Phase
Receiver Data
Compensation
FIFO
Parallel Clock (Recovered Clock)
RX
Phase
Receiver Data
Compensation
FIFO
Parallel Clock (Recovered Clock)
RX
Phase
Receiver Data
Compensation
FIFO
Parallel Clock (Recovered Clock)
Receiver Data
rx_clkout[1]/tx_clkout[1]
Receiver Data
rx_clkout[0]/tx_clkout[0]
Receiver Data
Receiver Data
rx_clkout[0]
Receiver Data
FPGA Fabric
Channel 1 Receiver
Data and Status Logic
rx_coreclkin[1]
Channel 0 Receiver
Data and Status Logic
rx_coreclkin[0]
FPGA Fabric
Channel 2 Receiver
Data and Status Logic
rx_coreclkin[2]
Channel 1 Receiver
Data and Status Logic
rx_coreclkin[1]
Channel 0 Receiver
Data and Status Logic
rx_coreclkin[0]
Transceiver Clocking in Cyclone V Devices
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CV-53002
2013.05.06