Ecc And Parity Control; Preloader Handoff Information - Altera Cyclone V Device Handbook

cv_54014
2013.12.30
You can set the individual disable register (indiv) to disable the following interfaces between the FPGA
and HPS:
• Reset request interface
• JTAG enable interface
• I/O configuration interface
• Boundary scan interface
• Debug interface
• Trace interface
• System Trace Macrocell (STM) interface
• Cross-trigger interface (CTI)
• NAND interface
• SD/MMC interface
• SPI Master interface
• EMAC interfaces

ECC and Parity Control

The system manager can enable or disable ECC for each of the following HPS modules with ECC-protected
RAM:
• MPU L2 cache data RAM
• On-chip RAM
• USB 2.0 OTG controller (USB0 and USB1) RAM
• EMAC (EMAC0, EMAC1, and EMAC2) RAM
• DMA controller RAM
• CAN controller RAM
• NAND flash controller RAM
• Quad SPI flash controller RAM
• SD/MMC controller RAM
• DDR interfaces
The system manager can inject single-bit or double-bit errors into the MPU L2 ECC memories for testing
purposes. Set the bits in the appropriate memory enable register to inject errors. For example, to inject a
single bit EEC error, set the injs bit of the mpu_ctrl_l2_ecc register.
The system manager can also inject parity failures into the parity-protected RAM in the MPU L2 to test the
parity failure interrupt handler. Set the bits of the parity fail injection register (parityinj) to inject parity
failures.

Preloader Handoff Information

The system manager provides eight 32-bit registers to store handoff information between the preloader and
the operating system. The preloader can store any information in these registers. These register contents
have no impact on the state of the HPS hardware. When the operating system kernel boots, it retrieves the
information by reading the preloader to OS handoff information register array. These registers are reset only
by a cold reset.
System Manager
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ECC and Parity Control
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