Altera Cyclone V Device Handbook page 706

11-28
Clocks
Clock Name
sdmmc_sample_clk
sdmmc_drv_clk
Figure 11-10: SD/MMC Controller Clock Connections
l4_mp_clk
sdmmc_clk
The sdmmc_clk clock from the clock manager is divided by four and becomes the sdmmc_clk_divided
clock before passing to the phase shifters and the SD/MMC controller CIU. The phase shifters are used to
generate the sdmmc_drv_clk and sdmmc_sample_clk clocks. These phase shifters provide up to
eight phases shift which include 0, 45, 90, 135, 180, 225, 270, and 315 degrees. The sdmmc_sample_clk
clock can be driven by the output from the phase shifter.
Note: The selections of phase shift degree and sdmmc_sample_clk source are done in the system
manager. For information about setting the phase shift and selecting the source of the
sdmmc_sample_clk clock, refer to the Clock Setup section within this document.
The controller generates the sdmmc_cclk_out clock, which is driven to the card. For more information
about the generation of the sdmmc_cclk_out clock, refer to the Clock Control Block section within this
document.
Related Information
• Clock Setup
Refer to this section for information about setting the phase shift.
• Clock Control Block
Refer to this section for information about the generation of the sdmmc_cclk_outclock.
Altera Corporation
Direction
Internal
Internal
sdmmc_clk_divided
Divide
by 4
sdmmc_drv_clk
Phase
Shifter
sdmmc_sample_clk
Phase
Shifter
on page 11-25
Description
Phase-shifted clock of sdmmc_clk_divided
used to sample the command and data from the
card
Phase-shifted clock of sdmmc_clk_divided
for controller to drive command and data to the
card to meet hold time requirements
sdmmc_cclk_out
SD/MMC
Controller
Core
cv_54011
2013.12.30
SD/MMC Controller
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