Altera Cyclone V Device Handbook page 172

CV-52005
2014.01.10
Date
I/O Features in Cyclone V Devices
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Added link to the known document issues in the Knowledge Base.
Updated the M386 package to M383.
Updated the M383 package plan of the Cyclone V E device.
Updated the GPIO count for the M301 package of the Cyclone V GX
devices.
Updated the HPS I/O counts for Cyclone V SE, SX, and ST devices.
Updated the I/O vertical migration table.
Corrected the note in the MultiVolt I/O interface topic.
Updated the 3.3 V LVTTL programmable current strength values to
add 16 mA current strength.
Removed statements indicating that the clock tree network cannot cross
over to different I/O regions.
Removed references to
apply to Cyclone V devices.
Added Bank 1A to the I/O banks location figure for Cyclone V E devices
because it is now available for the Cyclone V E A2 and A4 devices.
Added the M383 and M484 packages to the modular I/O banks tables
for Cyclone V E devices, and added the U484 package for the Cyclone V
E A9 device.
Added the U324, M301, M383, and M484 to the modular I/O banks
tables for the Cyclone V GX devices, and added the U484 package for
the Cyclone V GX C9 device.
Added the M301, M383, and M484 to the modular I/O banks tables for
the Cyclone V GT devices, and added the U484 package for the
Cyclone V GT D9 device.
Added notes to clarify the HPS row and column I/O counts in the
modular I/O banks tables for the Cyclone V SE, SX, and ST devices.
Changed the color of the transceiver blocks in the high-speed differential
I/O location diagrams for clarity.
Repaired the diagram for the example of calibrating multiple I/O banks
with a shared OCT calibration block for readability.
Added a topic about emulated LVDS buffers.
Edited the topic about true LVDS buffers.
Document Revision History
Changes
port because the port does not
rx_syncclock
5-75
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