Altera Cyclone V Device Handbook page 817

cv_54016
2013.12.30
When a DMA channel thread in the Non-secure state processes the following instructions:
• DMAWFE The DMAC uses the status of the corresponding INS bit, in the CR3 register, to control if it
waits for the event.
• If INS = 0 The event is in the Secure state. The DMAC:
• Executes an NOP.
• Sets the appropriate bit in the FSRC register that corresponds to the DMA channel number.
• Sets the ch_evnt_err bit in the FTRn register.
• Moves the DMA channel to the Faulting completing state.
• If INS = 1 The event is in the Non-secure state. The DMAC halts execution of the thread and waits
for the event to occur.
• DMASEV The DMAC uses the status of the corresponding INS bit, in the CR3 register, to control if it
creates the event.
• If INS = 0 The event-interrupt resource is in the Secure state. The DMAC:
• Executes an NOP.
• Sets the appropriate bit in the FSRC register that corresponds to the DMA channel number.
• Sets the ch_evnt_err bit in the FTRn register.
• Moves the DMA channel to the Faulting completing state.
• If INS = 1 The event-interrupt resource is in the Non-secure state. The DMAC creates the event
interrupt.
• DMAWFP The DMAC uses the status of the corresponding PNS bit, in the CR4 register, to control if it
waits for the peripheral to signal a request.
• If PNS = 0 The peripheral is in the Secure state. The DMAC:
• Executes an NOP.
• Sets the appropriate bit in the FSRC register that corresponds to the DMA channel number.
• Sets the ch_periph_err bit in the FTRn register.
• Moves the DMA channel to the Faulting completing state.
• If PNS = 1 The peripheral is in the Non-secure state. The DMAC halts execution of the thread and
waits for the peripheral to signal a request.
• DMALDP and DMASTP The DMAC uses the status of the corresponding PNS bit, in the CR4 register,
to control if it sends an acknowledgement to the peripheral.
• If PNS = 0 The peripheral is in the Secure state. The DMAC:
• Executes an NOP.
• Sets the appropriate bit in the FSRC register that corresponds to the DMA channel number.
• Sets the ch_periph_err bit in the FTRn register.
• Moves the DMA channel to the Faulting completing state.
• If PNS = 1 The peripheral is in the Non-secure state. The DMAC sends a message to the peripheral
to communicate when the data transfer is complete.
DMA Controller
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DMA Channel Thread in Non-Secure State
16-21
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