Functional Description Of The Usb Otg Controller; Usb Otg Controller Block Description - Altera Cyclone V Device Handbook

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Functional Description of the USB OTG Controller

Figure 18-2: USB OTG Controller Block Description

Details about each of the units that comprise the USB OTG controller are shown below.

Master Interface

The master interface includes a built-in DMA controller. The DMA controller moves data between external

memory and the media access controller (MAC).

Properties of the master interface are controlled through the USB L3 Master HPROT Register (l3master)

in the system manager. These bits provide access information to the L3 interconnect, including whether or

not transactions are cacheable, bufferable, or privileged.

Bits in the l3master register can be updated only when the master interface is guaranteed to be

in an inactive state.

Slave Interface

The slave interface allows other masters in the system to access the USB OTG controller's CSRs. For testing

purposes, other masters can also access the SPRAM.

Slave Interface CSR Unit

The slave interface can read from and write to all the CSRs in the USB OTG controllers. All register accesses

are 32 bits.

USB 2.0 OTG Controller

Send Feedback

Functional Description of the USB OTG Controller

L3 Interconnect

Master Interface

Application Interface Unit

Packet FIFO Controller

Media Access Controller

Wakeup and PHY Controller

PHY Interface

External USB Transceiver

Slave Interface

ULPI PHY Interface

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