Altera Cyclone V Device Handbook page 143

5-46
Single-ended I/O Termination
Figure 5-20: SSTL I/O Standard Termination
This figure shows the details of SSTL I/O termination on Cyclone V devices.
Termination
External
On-Board
Termination
OCT Transmit
OCT Receive
OCT in
Bidirectional
Pins
Altera Corporation
SSTL Class I
V
TT
50 Ω
25 Ω
50 Ω
V REF
Transmitter
V
TT
Series OCT 50 Ω
50 Ω
50 Ω
V REF
Transmitter
V
25 Ω
50 Ω
V REF
Transmitter
V
CCIO
Series
V REF
OCT 50 Ω
100 Ω
50 Ω
100 Ω
GND
V REF
FPGA
Receiver Transmitter
Series OCT 25 Ω
Receiver Transmitter
FPGA
CCIO
Parallel OCT
100 Ω
100 Ω
GND
Receiver Transmitter
V
CCIO
Series
OCT 25 Ω
100 Ω
100 Ω
Series
GND
OCT 50 Ω
FPGA FPGA
SSTL Class II
V V
TT TT
50 Ω 50 Ω
50 Ω
25 Ω
V REF
Receiver
V V
TT TT
50 Ω 50 Ω
50 Ω
V REF
Receiver
V
TT
V
CCIO
Parallel OCT
50 Ω
100 Ω
50 Ω
25 Ω
V REF
100 Ω
GND
Receiver
V V
CCIO CCIO
V REF
100 Ω 100 Ω
50 Ω
100 Ω 100 Ω
Series
GND GND
V REF OCT 25 Ω
FPGA
I/O Features in Cyclone V Devices
CV-52005
2014.01.10
FPGA
Send Feedback