Altera Cyclone V Device Handbook page 669

cv_54010
2013.12.30
1. time_out All other interrupt bits are set to 0 when the watchdog time_out bit is asserted.
2. dma_cmd_comp This interrupt status bit is the last to be asserted during a DMA operation to transfer
data. This bit signifies the completion of data transfer sequence.
3. pipe_cpybck_cmd_comp This bit is asserted when a copyback command or the last page of a
pipeline command completes.
4. locked_blk This bit is asserted when a program (or erase) is performed on a locked block.
5. INT_act No relationship with other interrupt status bits. Indicates a transition from 0 to 1 on the
ready_busy pin value for that flash device.
6. rst_comp No relationship with other interrupt status bits. Occurs after a reset command has completed.
7. For an erase command:
a. erase_fail (if failure)
b. erase_comp
8. For a program command:
a. locked_blk (if performed on a locked block)
b. pipe_cmd_err (if the pipeline sequence is broken by a MAP01 command)
c. page_xfer_inc (at the end of each page data transfer)
d. program_fail (if failure)
e. pipe_cpybck_cmd_comp
f. program_comp
g. dma_cmd_comp (If DMA enabled)
9. For a read command:
a. pipe_cmd_err (if the pipeline sequence is broken by a MAP01 command)
b. page_xfer_inc (at the end of each page data transfer)
c. pipe_cpybck_cmd_comp
d. load_comp
e. ecc_uncor_error (if failure)
f. dma_cmd_comp (If DMA enabled)
Timing Registers
You must optimize the following registers for your flash device's speed grade and clock frequency. The
NAND flash controller operates correctly with the power-on reset values. However, functioning with
power-on reset values is a non-optimal mode that provides loose timing (large margins to the signals).
Set the following registers in the config group to optimize the NAND flash controller for the speed grade
of the connected device and frequency of operation of the flash controller:
• twhr2_and_we_2_re
• tcwaw_and_addr_2_data
• re_2_we
• acc_clks
• rdwr_en_lo_cnt
• rdwr_en_hi_cnt
• max_rd_delay
• cs_setup_cnt
• re_2_re
NAND Flash Controller
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Timing Registers
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