Altera Cyclone V Device Handbook page 845

cv_54016
2013.12.30
Figure 16-29: Unaligned to Aligned Program
The first DMALD instruction does not load sufficient data to enable the DMAC to execute a DMAST and
therefore the program includes an additional DMALD, prior to the start of the loop.
After the first DMALD, the subsequent DMALDs align with the source burst size. This optimizes the p
performance but it requires a larger number of MFIFO buffer entries.
Note:
The DMALD shown as d does not increase the MFIFO buffer usage because it loads four bytes into
an MFIFO buffer entry that the DMAC has already allocated to this channel.
This example has a static requirement of four MFIFO buffer entries and a dynamic requirement of four
MFIFO buffer entries.
Unaligned Source Address to Aligned Destination Address with Excess Initial Load
This program is an alternative to that described in Unaligned Source Address to Aligned Destination Address.
The program executes a different sequence of source bursts which might be less efficient, but require fewer
MFIFO buffer entries.
DMAMOV CCR, SB5 SS64 DB4 DS64
DMAMOV SAR, 0x1004
DMAMOV DAR, 0x4000
DMALD ; shown as a in the figure below
DMAST ; shown as b in the figure below
DMAMOV CCR, SB4 SS64 DB4 DS64
DMALP 14
DMALD ; shown as c and cn in the figure below
DMALPEND
DMAMOV CCR, SB3 SS64 DB4 DS64
DMALD ; shown as e in the figure below
DMAMOV CCR, SB1 SS32 DB4 DS64
DMALD ; shown as f in the figure below
DMA Controller
Send Feedback
Unaligned Source Address to Aligned Destination Address with Excess Initial Load
b b b n
1
8
a d
4
c c c
0
Data from
DMALD
DMALD
7
a a a a a a a a
a a a a a a a a
Data for
a a a a a a a a
first DMAST
b b b b
1 1 1
b b b b
1 1 1
b b b b
1 1 1
b b b b
1 1 1
Data for
b b b b b
14x DMAST
e
b b b b
n n n
b b b b
n n n
Data for
b b b b
n n n
last DMAST
d d d d b
DMAST
0
a a a a
1
b b b b
1 1 1 1 1
b b b b
1 1 1 1 1
b b b b
1 1 1 1 1
b b b
1 1 1 1
b b b b
n n n n n
b b b b
n n n n n
b b b b
n n n n n
b b b
n n n n
Altera Corporation
16-49