Embedded Memory Configurations - Altera Cyclone V Device Handbook

2-8

Embedded Memory Configurations

Power-up state
Asynchronous clears
Write/read operation triggering
Same-port read-during-write
Mixed-port read-during-write
ECC support
Related Information
Internal Memory (RAM and ROM) User Guide
Provides more information about the embedded memory features.
Embedded Memory Configurations
Table 2-6: Supported Embedded Memory Block Configurations for Cyclone V Devices
This table lists the maximum configurations supported for the embedded memory blocks. The information is
applicable only to the single-port RAM and ROM modes.
Memory Block
MLAB
M10K
Altera Corporation
Features M10K
Output ports are
cleared.
Output registers and
output latches
Rising clock edges
Output ports set to
"new data" or "don't
care".
(The "don't care" mode
applies only for the
single-port RAM
mode).
Output ports set to "old
data" or "don't care".
Soft IP support using
the Quartus II
software.
Depth (bits)
32
256
512
1K
2K
4K
8K
Embedded Memory Blocks in Cyclone V Devices
MLAB
Registered output
ports—Cleared.
Unregistered output ports—Read
memory contents.
Output registers and output latches
Rising clock edges
Output ports set to "don't care".
Output ports set to "old data", "new
data", "don't care", or "constrained
don't care".
Soft IP support using the Quartus II
software.
Programmable Width
x16, x18, or x20
x40 or x32
x20 or x16
x10 or x8
x5 or x4
x2
x1
Send Feedback
CV-52002
2013.05.06