Altera Cyclone V Device Handbook page 956

cv_54020
2013.12.30
defined to be a high-to-low transition of the SDA signal while SCL is 1. When the master wants to terminate
the transmission, the master issues a STOP condition. This is defined to be a low-to-high transition of the
SDA line while SCL is 1. †
The following figure shows the timing of the START and STOP conditions. When data is being transmitted
on the bus, the SDA line must be stable when SCL is 1. †
Figure 20-3: Timing Diagram for START and STOP Conditions
SDA
SCL
Start
Condition
The signal transitions for the START or STOP condition, as shown in the figure, reflect those observed at
the output signals of the master driving the I
signals at the input signals of the slave(s), because unequal line delays may result in an incorrect SDA or
SCL timing relationship. †
Addressing Slave Protocol
7-Bit Address Format
During the 7-bit address format, the first seven bits (bits 7:1) of the first byte set the slave address and the
LSB bit (bit 0) is the R/W bit as shown in the following figure. When bit 0 (R/W) is set to 0, the master writes
to the slave. When bit 0 (R/W) is set to 1, the master reads from the slave. †
Figure 20-4: 7- Bit Address Format
10-Bit Address Format
During 10-bit addressing, two bytes are transferred to set the 10-bit address. The transfer of the first byte
contains the following bit definition. The first five bits (bits 7:3) notify the slaves that this is a 10-bit transfer
followed by the next two bits (bits 2:1), which set the slaves address bits 9:8, and the LSB bit (bit 0) is the
R/W bit. The second byte transferred sets bits 7:0 of the slave address. †
I2C Controller
Send Feedback
S
Data Change
Allowed
MSB
S A6
S: Start Condition
R/W: Read/Write Pulse
ACK: Acknowledge (Sent by Slave)
Data Line Stable
Data Valid
2
C bus. Care should be taken when observing the SDA or SCL
A5 A4 A3 A2 A1
Slave Address
Addressing Slave Protocol
P
Data Change Stop
Allowed Condition
LSB
A0 R/W ACK
20-5
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