Altera Cyclone V Device Handbook page 630

8-30
Analysis of Debug Report
• The Read Deskew and Write Deskew results shown in the debug report are before calibration. (Before
calibration results are actually from the window seen during calibration, and are most useful for debugging.)
• For each DQ group, the Write Deskew, Read Deskew, DM Deskew, and Read after Write results map to
the before-calibration margins reported in the EMIF Debug Toolkit.
Note: The Write Deskew, Read Deskew, DM Deskew, and Read after Write results are reported in delay
steps (nominally 25ps, in Arria V and Cyclone V devices), not in picoseconds.
For more information about calibration, refer to Calibration Stages in the Functional Description—UniPHY
chapter, in the External Memory Interface Handbook.
• DQS Enable calibration is reported as a VFIFO setting (in one clock period steps), a phase tap (in one-
eighth clock period steps), and a delay chain step (in 25ps steps).
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; Start
Delay 4
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; End
Delay 9
SEQ.C: DQS Enable ; Group 0 ; Rank 0 ; Center VFIFO
Delay 1
Analysis of DQS Enable results: A VFIFO tap is 1 clock period, a phase is 1/8 clock period (45 degrees)
and delay is nominally 25ps per tap. The DQSen window is the difference between the start and end for
the above example, assuming a frequency of 400 MHz (2500ps), that calculates as follows: start is
5*2500 + 6*2500/8 +4*25 = 14475ps. By the same calculation, the end is 16788ps.
Consequently, the DQSen window is 2313ps.
• The size of a read window or write window is equal to (left edge + right edge) * delay
chain step size. Both the left edge and the right edge can be negative or positive.:
SEQ.C: Read Deskew
27 ; DQ delay
SEQ.C: Write Deskew ; DQ
17 ; DQ delay
Analysis of DQ and DQS delay results: The DQ and DQS output delay (write) is the D5 delay chain. The
DQ input delay (read) is the D1 delay chain, the DQS input delay (read) is the D4 delay chain.
Altera Corporation
; DQ 0 ; Rank 0 ; Left edge
0 ; DQS delay 8
0 ; Rank 0 ; Left edge
6 ; DQS delay 4
VFIFO 5 ; Phase 6 ;
VFIFO 6 ; Phase 5 ;
6 ; Phase 2 ;
18 ; Right edge
30 ; Right edge
SDRAM Controller Subsystem
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2013.12.30