Altera Cyclone V Device Handbook page 3

Byte Enable in Embedded Memory Blocks............................................................................................2-13
Byte Enable Controls in Memory Blocks....................................................................................2-13
Data Byte Output...........................................................................................................................2-14
RAM Blocks Operations...............................................................................................................2-15
Memory Blocks Packed Mode Support..................................................................................................2-15
Memory Blocks Address Clock Enable Support....................................................................................2-15
Document Revision History.....................................................................................................................2-17
Variable Precision DSP Blocks in Cyclone V Devices........................................3-1
Features.........................................................................................................................................................3-1
Supported Operational Modes in Cyclone V Devices............................................................................3-2
Resources.......................................................................................................................................................3-3
Design Considerations................................................................................................................................3-4
Operational Modes..........................................................................................................................3-4
Internal Coefficient and Pre-Adder...............................................................................................3-4
Accumulator.....................................................................................................................................3-4
Chainout Adder................................................................................................................................3-4
Block Architecture.......................................................................................................................................3-5
Input Register Bank.........................................................................................................................3-6
Pre-Adder..........................................................................................................................................3-8
Internal Coefficient..........................................................................................................................3-8
Multipliers.........................................................................................................................................3-8
Adder.................................................................................................................................................3-9
Accumulator and Chainout Adder................................................................................................3-9
Systolic Registers............................................................................................................................3-10
Double Accumulation Register....................................................................................................3-10
Output Register Bank....................................................................................................................3-10
Operational Mode Descriptions..............................................................................................................3-10
Independent Multiplier Mode.....................................................................................................3-11
Independent Complex Multiplier Mode....................................................................................3-13
Multiplier Adder Sum Mode........................................................................................................3-15
18 x 18 Multiplication Summed with 36-Bit Input Mode........................................................3-15
Systolic FIR Mode..........................................................................................................................3-15
Document Revision History.....................................................................................................................3-18
Clock Networks and PLLs in Cyclone V Devices................................................4-1
Clock Networks............................................................................................................................................4-1
Clock Resources in Cyclone V Devices.........................................................................................4-2
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
TOC-3
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