Altera Cyclone V Device Handbook page 494

2-20
Clock Usage By Module
Module Name
I2C controller 2
I2C controller 3
UART controller 0
UART controller 1
CAN controller 0
CAN controller 1
GPIO interface 0
GPIO interface 1
GPIO interface 2
System manager
SDRAM subsystem
Altera Corporation
System Clock Name
l4_sp_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
can0_clk
l4_sp_clk
can1_clk
l4_mp_clk
gpio_db_clk
l4_mp_clk
gpio_db_clk
l4_mp_clk
gpio_db_clk
osc1_clk
l4_sp_clk
ddr_dq_clk
Use
Clock for the I2C 2
Clock for the I2C 3
Clock for the UART 0
Clock for the UART 1
Clock for the slave
CAN 0 controller clock
Clock for the slave
CAN 1 controller clock
Clock for the slave
Debounce clock
Clock for the slave
Debounce clock
Clock for the slave
Debounce clock
Clock for the system manager
Clock for the control slave
Off-chip data clock
Clock Manager
Send Feedback
cv_54002
2013.12.30