Altera Cyclone V Device Handbook page 577

cv_54006
2013.12.30
Parity logic
Lockdown by master
Lockdown by line
AXI ID width on slave ports
Address filtering
Speculative read
Presence of ARUSERMx and AWUSERMx sideband
signals
For further information about cache controller configurable options, refer to the CoreLink Level 2 Cache
Controller L2C-310 Technical Reference Manual, available on the ARM website (infocenter.arm.com).
Related Information
ARM Infocenter (www.infocenter.arm.com)
L2 Cache Lockdown Capabilities
The L2 cache has three methods to lock data in the cache RAMs:
• Lockdown by line Used to lock lines in the cache. This is commonly used for loading critical sections
of software into the cache temporarily.
• Lockdown by way Allows any or all of the eight cache ways to be locked. This is commonly used for
loading critical data or code into the cache.
• Lockdown by master Allows cache ways to be dedicated to a single master port. This allows a large
cache to look like smaller caches to multiple master ports. The L2 cache can be mastered by CPU0, CPU1,
or the six ACP masters, for a total of eight possible master ports.
For more information about L2 cache lockdown capabilities, refer to "Cache operation" in the Functional
Overview chapter of the CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, available
on the ARM website (infocenter.arm.com).
Related Information
ARM Infocenter (www.infocenter.arm.com)
L2 Cache Event Monitoring
The L2 cache supports the built-in cache event monitoring signals shown in
count two of the events at any one time.
Table 6-9: L2 Cache Events
CO
DRHIT
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
Feature
Event
L2 Cache Lockdown Capabilities
Meaning
Parity logic enabled
Lockdown by master enabled
Lockdown by line enabled
6 AXI ID bits on slave ports
Address filtering logic enabled
Logic for supporting speculative read enabled
Sideband signals enabled
Description
Eviction (cast out) of a line from the L2 cache.
Data read hit in the L2 cache.
6-31
Table 6-9. The L2 cache can
Altera Corporation