Altera Cyclone V Device Handbook page 829

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to the peripheral that the data transfer is complete. If the src_inc bit in the channel control registers is

set to incrementing, the DMAC updates source address registers after it executes DMALDP<S|B>.

Figure 16-12: DMALDP<S|B> Instruction Encoding

Assembler syntax

DMALDP<S|B> <peripheral>

<S> When S is present, the assembler sets bs to 0. The instruction is conditional on the state of the

request_type flag:

• request_type = Single

The DMAC performs a DMALDP instruction and it sets arlen[3:0]=0x0 so that the AXI read transaction

length is one. The DMAC ignores the value of the src_burst_len field in the channel control registers.

• request_type = Burst

The DMAC performs a DMANOP.

<B> When B is present, the assembler sets bs to 1. The instruction is conditional on the state of the

request_type flag:

• request_type = Single

The DMAC performs a DMANOP.

• request_type = Burst

The DMAC performs a load using a burst DMA transfer.

<peripheral> 5-bit immediate, value 0-31.

The DMAC sets the value of the request_type flag when it executes a DMAWFP instruction.

You can only use this instruction in a DMA channel thread. Execution of the instruction is conditional on

the state of the request_type flag matching that of the instruction.

Loop instructs the DMAC to load an 8-bit value into the loop counter register you specify.

This instruction indicates the start of a section of instructions, and you set the end of the section using the

DMALPEND instruction. The DMAC repeats the set of instructions that you insert between DMALP and

DMALPEND until the value in the loop counter register reaches zero.

The DMAC saves the value of the PC for the instruction that follows DMALP. After the DMAC

executes DMALPEND, and the loop counter register is not zero, this enables it to execute the first

instruction in the loop.

DMA Controller

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