Altera Cyclone V Device Handbook page 54

3-16
18-Bit Systolic FIR Mode
Figure 3-13: Basic FIR Filter Equation
Depending on the number of taps and the input sizes, the delay through chaining a high number of adders
can become quite large. To overcome the delay performance issue, the systolic form is used with additional
delay elements placed per tap to increase the performance at the cost of increased latency.
Figure 3-14: Systolic FIR Filter Equivalent Circuit
Cyclone V variable precision DSP blocks support the following systolic FIR structures:
18-bit
27-bit
In systolic FIR mode, the input of the multiplier can come from four different sets of sources:
Two dynamic inputs
One dynamic input and one coefficient input
One coefficient input and one pre-adder output
One dynamic input and one pre-adder output
18-Bit Systolic FIR Mode
In 18-bit systolic FIR mode, the adders are configured as dual 44-bit adders, thereby giving 8 bits of overhead
when using an 18-bit operation (36-bit products). This allows a total of 256 multiplier products.
Altera Corporation
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Variable Precision DSP Blocks in Cyclone V Devices
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2014.01.10