Altera Cyclone V Device Handbook page 178

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DQ/DQS Bus Mode Pins for Cyclone V Devices

Differential or complementary DQS signaling—the maximum number of data pins per group decreases

DDR3 and DDR2 interfaces—each x8 group of pins require one DQS pin. You may also require one

DQSn pin and one DM pin. This further reduces the total number of data pins available.

Table 6-4: DQ/DQS Bus Mode Pins for Cyclone V Devices

Altera Corporation

DQSn Support

Maximum Data Pins per Group

External Memory Interfaces in Cyclone V Devices

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