Altera Cyclone V Device Handbook page 573

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HPS Peripheral Master Input IDs

Table 6-5: HPS Peripheral Master Input IDs

The input IDs issued from the interconnect for each HPS peripheral master that can access the ACP ID mapper

FPGA-to-HPS bridge

Control of the AXI User Sideband Signals

The ACP ID mapper module allows control of the AXI user sideband signal values. Not all masters drive

these signals, so the ACP ID mapper makes it possible to drive the 5-bit user sideband signal with either a

default value (in dynamic mode) or specific values (in fixed mode).

There are registers available to configure the default values of the user sideband signals for all transactions,

and fixed values of these signals for particular transactions in fixed mapping mode. In dynamic mode, the

user sideband signals of incoming transactions are mapped with the default values stored in the register. In

fixed mapping mode, the input ID of the transaction is mapped to the 3-bit output ID and the user sideband

signals of the transaction are mapped with the values stored in the register that corresponds to the output

ID. One important exception, however, is that the ACP ID mapper always allows user sideband signals from

the FPGA-to-HPS bridge to pass through to the ACP regardless of the user sideband value associated with

Values are in binary. The letter x denotes variable ID bits each master passes with each transaction.

Cortex-A9 Microprocessor Unit Subsystem

Send Feedback

Interconnect Master

HPS Peripheral Master Input IDs

00000xxxx011

10000xxxx001

10000xxxx010

100000000011

100000000110

1xxxxxxxx100

100000000000

000000000001

100000000101

0xxxxxxxx100

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