Altera Cyclone V Device Handbook page 828

16-32
DMALD[S | B]
DMALD[S | B]
Load instructs the DMAC to perform a DMA load, using AXI transactions that the source address registers
and channel control registers specify. It places the read data into the MFIFO buffer and tags it with the
corresponding channel number. DMALD is an unconditional instruction but DMALDS and DMALDB are
conditional on the state of the request_type flag. If the src_inc bit in the channel control registers
is set to incrementing, the DMAC updates the source address registers after it executes DMALD[S|B].
Note: The DMAC sets the value of request_type when it executes a DMAWFP instruction.
Figure 16-11: DMALD[S|B] Instruction Encoding
Assembler syntax
DMALD[S|B]
where:
[S] If S is present, the assembler sets bs to 0 and x to 1. The instruction is conditional on the state of the
request_type flag:
• request_type = Single
The DMAC performs a DMALD instruction and it sets arlen[3:0]=0x0 so that the AXI read transaction
length is one. The DMAC ignores the value of the src_burst_len field in the channel control registers.
• request_type = Burst
The DMAC performs a DMANOP instruction. The DMAC increments the channel PC to the next instruction.
No state change occurs.
[B] If B is present, the assembler sets bs to 1 and x to 1. The instruction is conditional on the state of the
request_type flag:
• request_type = Single
The DMAC performs a DMANOP instruction. The DMAC increments the channel PC to the next instruction.
No state change occurs.
• request_type = Burst
The DMAC performs a DMALD.
If you do not specify the S or B operand, the assembler sets bs to 0 and x to 0, and the DMAC always executes
a DMA load.
Operation
You can only use this instruction in a DMA channel thread. If you specify the S or B operand, execution of
the instruction is conditional on the state of request_type matching that of the instruction.
DMALDP<S | B>
Load and notify Peripheral instructs the DMAC to perform a DMA load, using AXI transactions that source
address registers and channel control registers specify. It places the read data into a FIFO buffer that is tagged
with the corresponding channel number and after it receives the last data item, it sends an acknowledgement
Altera Corporation
7 6 5 4 3 2 1 0
0 0 0 0 1 bs x
0
cv_54016
2013.12.30
DMA Controller
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