Altera Cyclone V Device Handbook page 6

TOC-6
Cyclone V Device Handbook Volume 1: Device Interfaces and Integration
True LVDS Buffers in Cyclone V Devices..................................................................................5-55
Emulated LVDS Buffers in Cyclone V Devices.........................................................................5-63
Differential Transmitter in Cyclone V Devices.....................................................................................5-63
Transmitter Blocks.........................................................................................................................5-63
Serializer Bypass for DDR and SDR Operations.......................................................................5-64
Differential Receiver in Cyclone V Devices...........................................................................................5-65
Receiver Blocks in Cyclone V Devices........................................................................................5-65
Receiver Mode in Cyclone V Devices.........................................................................................5-67
Receiver Clocking for Cyclone V Devices..................................................................................5-68
Differential I/O Termination for Cyclone V Devices...............................................................5-68
Source-Synchronous Timing Budget......................................................................................................5-69
Differential Data Orientation.......................................................................................................5-69
Differential I/O Bit Position.........................................................................................................5-70
Transmitter Channel-to-Channel Skew.....................................................................................5-71
Receiver Skew Margin for LVDS Mode......................................................................................5-71
Document Revision History.....................................................................................................................5-73
External Memory Interfaces in Cyclone V Devices............................................6-1
External Memory Performance..................................................................................................................6-2
HPS External Memory Performance.........................................................................................................6-2
Memory Interface Pin Support in Cyclone V Devices............................................................................6-2
Guideline: Using DQ/DQS Pins....................................................................................................6-3
DQ/DQS Bus Mode Pins for Cyclone V Devices........................................................................6-3
DQ/DQS Groups in Cyclone V E..................................................................................................6-5
DQ/DQS Groups in Cyclone V GX...............................................................................................6-7
DQ/DQS Groups in Cyclone V GT...............................................................................................6-9
DQ/DQS Groups in Cyclone V SE..............................................................................................6-11
DQ/DQS Groups in Cyclone V SX..............................................................................................6-11
DQ/DQS Groups in Cyclone V ST..............................................................................................6-12
External Memory Interface Features in Cyclone V Devices................................................................6-12
UniPHY IP......................................................................................................................................6-12
External Memory Interface Datapath.........................................................................................6-13
DQS Phase-Shift Circuitry............................................................................................................6-13
PHY Clock (PHYCLK) Networks...............................................................................................6-21
DQS Logic Block............................................................................................................................6-24
Dynamic OCT Control.................................................................................................................6-26
IOE Registers..................................................................................................................................6-26
Delay Chains...................................................................................................................................6-28
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