Altera Cyclone V Device Handbook page 19

1-10
Shared Arithmetic Mode
Figure 1-9: ALM in Shared Arithmetic Mode for Cyclone V Devices
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a 3-input
adder. This significantly reduces the resources necessary to implement large adder trees or correlator
functions.
The shared arithmetic chain can begin in either the first or sixth ALM in a LAB.
Similar to carry chains, the top and bottom half of the shared arithmetic chains in alternate LAB columns
can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in
an LAB while leaving the other half available for narrower fan-in functionality. In every LAB, the column
is top-half bypassable; while in MLAB, columns are bottom-half bypassable.
The Quartus II Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in arithmetic or
shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long shared arithmetic
chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A
shared arithmetic chain can continue as far as a full column.
Altera Corporation
shared_arith_in
4-Input
LUT
datae0
4-Input
datac
datab LUT
dataa
4-Input
LUT
datad
datae1
4-Input
LUT
shared_arith_out
carry_in
labclk
reg0
reg1
reg2
reg3
carry_out
Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices
CV-52001
2014.01.10
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