Independent Clock Enables In Clocking Modes; Parity Bit In Memory Blocks; Byte Enable In Embedded Memory Blocks; Byte Enable Controls In Memory Blocks - Altera Cyclone V Device Handbook

CV-52002
2013.05.06

Independent Clock Enables in Clocking Modes

Independent clock enables are supported in the following clocking modes:
Read/write clock mode—supported for both the read and write clocks.
Independent clock mode—supported for the registers of both ports.
To save power, you can control the shut down of a particular register using the clock enables.
Related Information
Guideline: Control Clocking to Reduce Power Consumption

Parity Bit in Memory Blocks

Table 2-11: Parity Bit Support for the Embedded Memory Blocks
This table describes the parity bit support for the memory blocks.
The parity bit is the fifth bit associated with each
4 data bits in data widths of 5, 10, 20, and 40 (bits
4, 9, 14, 19, 24, 29, 34, and 39).
In non-parity data widths, the parity bits are
skipped during read or write operations.
Parity function is not performed on the parity bit.

Byte Enable in Embedded Memory Blocks

The embedded memory blocks support byte enable controls:
The byte enable controls mask the input data so that only specific bytes of data are written. The unwritten
bytes retain the values written previously.
The write enable (
on the RAM blocks. By default, the
the writing.
The byte enable registers do not have a
If you are using parity bits, on the M10K blocks, the byte enable function controls 8 data bits and 2 parity
bits; on the MLABs, the byte enable function controls all 10 bits in the widest mode.
The MSB and LSB of the
The byte enables are active high.

Byte Enable Controls in Memory Blocks

Table 2-12:
byteena
byteena[1:0]
11 (default)
Embedded Memory Blocks in Cyclone V Devices
Send Feedback
M10K
) signal, together with the byte enable (
wren
signal correspond to the MSB and LSB of the data bus, respectively.
byteena
Controls in x20 Data Width
Independent Clock Enables in Clocking Modes
The parity bit is the ninth bit associated with each
byte.
The ninth bit can store a parity bit or serve as an
additional bit.
Parity function is not performed on the parity bit.
byteena
signal is high (enabled) and only the
byteena
port.
clear
Data Bits Written
[19:10]
on page 2-7
MLAB
) signal, control the write operations
wren
[9:0]
2-13
signal controls
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