Nand Flash Controller Programming Model; Basic Flash Programming - Altera Cyclone V Device Handbook

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NAND Flash Controller Programming Model

Signal
ce_n
cle
re_n
rb
we_n
wp_n
The HPS I/O pins support a single x8 device.
NAND Flash Controller Programming Model
This section describes how the NAND flash controller is to be programmed by software running on the
microprocessor unit (MPU).
Note: If you write a configuration register and follow it up with a data operation that is dependent on the
value of this configuration register, Altera recommends that you read the value of the register before
performing the data operation. This read operation ensures that the posted write of the register is
completed and takes effect before the data operation is issued to the NAND flash controller.

Basic Flash Programming

This section describes the steps that must be taken by software to access and control NAND flash controller.
NAND Flash Controller Optimization Sequence
The software must configure the flash device for interrupt or polling mode, using the bank0 bit of the
rb_pin_enabled register in the config group. If the device is in polling mode, the software must also
program the additional registers, to select the times and frequencies of the polling. Program the following
registers in the config group:
• Set the rb_pin_enabled register to the desired mode of operation for each flash device.
• For polling mode, set the load_wait_cnt register to the appropriate value depending on the speed
of operation of the NAND flash controller, and the desired wait value.
• For polling mode, set the program_wait_cnt register to the appropriate value by software depending
on the speed of operation of the NAND flash controller, and the desired wait value.
• For polling mode, set the erase_wait_cnt register to the appropriate value by software depending
on the speed of operation of the NAND flash controller, and the desired wait value.
• For polling mode, set the int_mon_cyccnt register to the appropriate value by software depending
on the speed of operation of the NAND flash controller, and the desired wait value.
At any time, the software can change any flash device from interrupt mode to polling mode or vice-versa,
using the bank0 bit of the rb_pin_enabled register.
The software needs to ensure that the particular flash device does not have any outstanding transactions
before changing the mode of operation for that particular flash device.
Altera Corporation
Width
1 out
1 out
1 out
1 in
1 out
1 out
I/O
Output Active-low chip enable
Command latch enable
Active-low read enable signal
Ready/busy signal
Active-low write enable signal
Active-low write protect signal
cv_54010
2013.12.30
Description
NAND Flash Controller
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