Altera Cyclone V Device Handbook page 174

CV-52005
2014.01.10
Date
June 2012
February 2012
November 2011
October 2011
I/O Features in Cyclone V Devices
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Version
Removed statements about LVDS SERDES being available on top and
bottom banks only.
Removed the topic about LVDS direct loopback mode.
Updated the true LVDS buffers count for Cyclone V E, GX, and GT
devices.
Added the RSKM equation, description, and high-speed timing diagram.
2.0 Updated for the Quartus II software v12.0 release:
Restructured chapter.
Added "Design Considerations", "VCCIO Restriction", "LVDS
Channels", "Modular I/O Banks", and "OCT Calibration Block" sections.
Added Figure 5–3, Figure 5–4, Figure 5–5, Figure 5–6, and Figure 5–27.
Updated Table 5–1, Table 5–8, and Table 5–10.
Updated Figure 5–22 with emulated LVDS with external single resistor.
1.2 Updated Table 5–1, Table 5–2, Table 5–8, and Table 5–10.
Updated "I/O Banks" on page 5–8.
Minor text edits.
1.1 Updated Table 5–2.
Updated Figure 5–3, Figure 5–4.
Updated "Sharing an OCT Calibration Block on Multiple I/O Banks",
"High-Speed Differential I/O Interfaces", and "Fractional PLLs and
Cyclone V Clocking" sections.
1.0 Initial release.
Document Revision History
Changes
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