Altera Cyclone V Device Handbook page 576

6-30
ECC Support
• Memory Management Unit
ECC Support
The L2 cache has the option of using ECCs to protect against SEU errors in the cache RAM.
Enabling ECCs does not affect the performance of the L2 cache. The ECC bits are calculated only for writes
to the data RAM that are 64 bits wide (8 bytes, or one-quarter of the cache line length). The ECC logic does
not perform a read-modify-write when calculating the ECC bits. The ECC protection bits are not valid in
the following cases:
• Data is written that is not 64-bit aligned in memory
• Data is written that is less than 64 bits in width
In these cases the Byte Write Error interrupt is asserted. Cache data is still written when such an error occurs.
However, the ECC error detection and correction continues to function. Therefore, the cache data is likely
to be incorrect on subsequent reads.
To use ECCs, the software and system must meet the following requirements:
• L1 and L2 cache must be configured as write-back allocate for any cacheable memory region
• FPGA soft IP using the ACP must only perform the following types of data writes:
• 64-bit aligned in memory
• 64 bit wide accesses
For more information about SEU errors, refer to the System Manager chapter in the Cyclone V Device
Handbook, Volume 3.
Related Information
System Manager
Implementation Details
Table 6-8 shows the parameter settings for the cache controller.
Table 6-8: Cache Controller Configuration
Cache way size
Number of cache ways
Tag RAM write latency
Tag RAM read latency
Tag RAM setup latency
Data RAM write latency
Data RAM read latency
Data RAM setup latency
Altera Corporation
on page 6-8
on page 14-1
Feature Meaning
64 KB
8 ways
1
1
1
1
2
1
Cortex-A9 Microprocessor Unit Subsystem
cv_54006
2013.12.30
Send Feedback