Configuring Embedded Cross-Trigger Connections - Altera Cyclone V Device Handbook

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Table 7-10: csCTI Trigger Output Acknowledge Signals

The following table lists the trigger output pin acknowledge connections implemented for csCTI.

FPGA-CTI connects the debug system to the FPGA fabric. FPGA-CTI has all of its triggers available to the

FPGA fabric.

Configuring Embedded Cross-Trigger Connections

CTI interfaces are programmable through a memory-mapped register interface.

The specific registers are described in the CoreSight Components Technical Reference Manual, which you

can download from the ARM website (infocenter.arm.com).

To access registers in any CoreSight component through the debugger, the register offsets must be added

to the CoreSight component's base address. That combined value must then be added to the address at which

the ROM table is visible to the debugger (0x80000000).

Each CTI has two interfaces, the trigger interface and the channel interface. The trigger interface is the

interface between the CTI and other components. It has eight trigger signals, which are hardwired to other

components. The channel interface is the interface between a CTI and its CTM, with four bidirectional

channels. The mapping of trigger interface to channel interface (and vice versa) in a CTI is dynamically

configured. You can enable or disable each CTI trigger output and CTI trigger input connection individually.

For example, you can configure trigger input 0 in the FPGA-CTI to route to channel 3, and configure trigger

output 3 in the FPGA-CTI and trigger output 7 in CTI-0 in the MPU debug subsystem to route from channel

3. This configuration causes a trigger at trigger input 0 in FPGA-CTI to propagate to trigger output 3 in the

FPGA-CTI and trigger output 7 in CTI-0. Propagation can be single-to-single, single-to-multiple, multiple-

to-single, and multiple-to-multiple.

CoreSight Debug and Trace

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