Altera Cyclone V Device Handbook page 863

17-14
System Time Register Module
System Time Register Module
The 64-bit time is maintained in this module and updated using the input reference clock, osc1_clk. The
osc1_clk clock comes from the clock manager and the emac_ptp_ref_clk clock comes from the FPGA fabric.
This time is the source for taking snapshots (timestamps) of Ethernet frames being transmitted or received
at the PHY interface.
The system time counter can be initialized or corrected using the coarse correction method. In this method,
the initial value or the offset value is written to the Timestamp Update register. For initialization, each
EMAC's system time counter is written with the value in the Timestamp Update registers, while for system
time correction, the offset value is added to or subtracted from the system time.
In the fine correction method, a slave clock's frequency drift with respect to the master clock is corrected
over a period of time instead of in one clock, as in coarse correction. This helps maintain linear time and
does not introduce drastic changes (or a large jitter) in the reference time between PTP sync message
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intervals.
In this method, an accumulator sums up the contents of the Timestamp_Addend register, as shown in the
figure below. The arithmetic carry that the accumulator generates is used as a pulse to increment the system
time counter. The accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high-
precision frequency multiplier or divider.
Note: You must connect a PTP clock with a frequency higher than the frequency required for the specified
accuracy.
Figure 17-4: Algorithm for System Time Update Using Fine Method
The System Time Update logic requires a 50 MHz clock frequency to achieve 20-ns accuracy. The frequency
division ratio (FreqDivisionRatio) is the ratio of the reference clock frequency to the required clock frequency.
Altera Corporation
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addend_val[31:0]
Addend Register
incr_sub_sec_reg
addend_updt
Accumulator Register
Constant Value
Sub-Second Register
incr_sec_reg
Second Register
Ethernet Media Access Controller
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2013.12.30