Altera Cyclone V Device Handbook page 791

15-4
Scan Manager Block Diagram and System Integration
The ARM JTAG-AP supports up to eight scan chains. The scan manager uses only scan chains 0, 1, 2, 3, and
7.
Scan chain 7 of the JTAG-AP connects to FPGA JTAG TAP controller. When the system manager undergoes
a cold reset, this connection is disabled and the FPGA JTAG pins are connected to the FPGA JTAG TAP
controller. You can configure the system manager to enable the connection, which allows software running
on the HPS to communicate with the FPGA JTAG TAP controller. In this case, software can send JTAG
commands (such as the SHIFT_EDERROR_REG JTAG instruction) to the FPGA JTAG and get responses
to determine details about CRC errors detected by the control block when the FPGA fabric is in user mode.
Through the FPGA manager, software can determine that a CRC error was detected. For more information
about the TAP controller, refer to the Communicating with the JTAG TAP Controller section of this chapter.
Scan chains 0 to 3 of the JTAG-AP connect to the configuration information in the HPS I/O scan chain
banks through the I/O configuration shift register (IOCSR) multiplexer. For more information, refer to the
Configuring HPS I/O Scan Chains section of this chapter.
Note: The I/O scan chains do not use the JTAG protocol. The scan manager uses the JTAG-AP as a parallel-
to-serial converter for the I/O scan chains. The I/O scan chains are connected only to the serial output
data (TDI JTAG signal) and serial clock (TCK JTAG signal).
The HPS I/O pins are divided into six banks. Each I/O bank is either a vertical (VIO) or horizontal (HIO)
I/O, based on its location on the die.
Table 15-2: Bank Usage of IOCSR Scan Chains
The following table shows the mapping of the IOCSR scan chains to the I/O banks.
IOCSR Scan Chain
0
1
2
3
When the FPGA JTAG TAP controller is in CONFIG_IO mode, the controller can override the scan manager
JTAG-AP and configure the HPS I/O pins. For more information, refer to the Configuring HPS I/O Scan
Chains section of this chapter.
Note: CONFIG_IO mode is commonly used to configure the I/O pin properties prior to performing
boundary scan testing.
Related Information
• Configuring HPS I/O Scan Chains
• Communicating with the JTAG TAP Controller
Altera Corporation
Bank Type
VIO
VIO
VIO
HIO
on page 15-5
HPS I/O Bank
I/O bank 7D and I/O bank
7E
I/O bank 7B and I/O bank
7C
I/O bank 7A
I/O bank 6
on page 15-6
cv_54015
2013.12.30
Usage
EMAC
SD/MMC, NAND, and
quad SPI
Trace, SPI, UART, I2C,
and CAN
SDRAM DDR
Scan Manager
Send Feedback