Altera Cyclone V Device Handbook page 651

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2013.12.30
high-performance data transfer mode. On receipt of erroneous commands (MAP00, MAP01 or MAP11),
the flash controller issues an unsup_cmd interrupt to inform the host about the violating command.
When the host issues a data DMA command the NAND flash controller transfers data between the flash
device and host memory if data DMA is enabled (the flag bit of the dma_enable register in the dma
group is set to 1). On the completion of the transfer the flash controller informs the host by asserting an
interrupt.
• A data DMA command is a type of MAP10 command. This command is interpreted by the data DMA
engine and not by the flash controller core.
• No MAP01, MAP00, or MAP11 commands are allowed when DMA is enabled.
• Before the flash controller can accept data DMA commands, DMA must be enabled by setting the flag
bit of the dma_enable register in the dma group.
• When DMA is enabled and the DMA engine initiates data transfers, ECC can be enabled for as-needed
data correction concurrent with the data transfer.
• MAP10 commands are used along with data movements similar to MAP01 commands.
• With the exception of data DMA commands and MAP10 pipeline read and write commands, all other
MAP10 commands such as erase, lock, unlock, and copy-back are forwarded to the flash controller.
• At any time, up to four outstanding data DMA commands can be handled by flash controller. During
multi-page operations, the DMA transfer must not cross a flash block boundary. If it does, the flash
controller generates an unsupported command (unsup_cmd) interrupt and drops the command.
• Data DMA commands are typically multi-page read and write commands with an associated pointer in
host memory. The multi-page data is transferred to or from the host memory starting from the host
memory pointer.
• Data DMA uses the flash_burst_length register in the dma group to determine the burst length
value to drive on the interconnect. The data DMA hardware does not account for the interconnect's
boundary crossing restrictions. The host must initialize the starting host address so that the DMA master
burst does not cross a 4 KB boundary.
There are two methods for initiating a DMA transaction: the multitransaction DMA command, and the
burst DMA command.
Multitransaction DMA Command
The NAND flash controller processes multitransaction DMA commands only if it receives all four
command-data pairs in order. The flash controller responds to out-of-order commands with an unsup_cmd
interrupt. The flash controller also responds with an unsup_cmd interrupt if sequenced commands are
interleaved with other flash controller MAP commands.
To initiate DMA with a multitransaction DMA command, you send four command-data pairs to the NAND
flash controller's data and control slave port, as shown in Command-Data Pair Formats.
Related Information
Command-Data Pair Formats
Command-Data Pair Formats
Related Information
• Indexed Addressing
• Burst DMA Command
NAND Flash Controller
Send Feedback
on page 10-13
on page 10-5
on page 10-15
Multitransaction DMA Command
10-13
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