Altera Cyclone V Device Handbook page 36

2-16
Memory Blocks Address Clock Enable Support
Figure 2-7: Address Clock Enable
This figure shows an address clock enable block diagram. The address clock enable is referred to by the port
name
addressstall
Figure 2-8: Address Clock Enable During Read Cycle Waveform
This figure shows the address clock enable waveform during the read cycle.
Altera Corporation
.
address[0]
address[N]
addressstall
clock
inclock
rdaddress
a0 a1
rden
addressstall
latched address
an a0
(inside memory)
q (synch) doutn-1 doutn
doutn dout0
q (asynch)
1
address[0]
address[0]
0
register
1
address[N]
address[N]
register
0
a2 a3 a4
a1
dout0 dout1
dout1
Embedded Memory Blocks in Cyclone V Devices
a5
a6
a4 a5
dout4
dout4
dout5
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CV-52002
2013.05.06