Altera Cyclone V Device Handbook page 353

CV-53002
2013.05.06
Block
Receiver (RX) phase
compensation FIFO
Receiver Non-Bonded Channel Configurations
This section describes the receiver non-bonded channel configurations.
The receiver clocking in non-bonded mode varies depending on whether the rate match FIFO is enabled.
When the rate match FIFO is not enabled, the receiver PCS in every channel uses the parallel recovered
clock. When the rate match FIFO is enabled, the receiver PCS in every channel uses both the parallel recovered
clock and parallel clock from the clock divider.
Transceiver Clocking in Cyclone V Devices
Send Feedback
Side
Write Parallel clock (divided). This clock is also forwarded to the
FPGA fabric.
Read Clock sourced from the FPGA fabric
Receiver Non-Bonded Channel Configurations
Clock Source
2-15
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