Altera Cyclone V Device Handbook page 330

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2013.05.06
In a link where the upstream transmitter and local receiver can be clocked with independent reference clock
sources, the data can be corrupted by any frequency differences (in ppm count) when crossing the data from
the recovered clock domain—the same clock domain as the upstream transmitter reference clock—to the
local receiver reference clock domain.
The rate match FIFO is 20 words deep, which compensates for the small clock frequency differences of up
to ±300 ppm (600 ppm total) between the upstream transmitter and the local receiver clocks by performing
symbol insertion or deletion, depending on the ppm difference on the clocks.
The rate match FIFO requires that the transceiver channel is in duplex configuration (both transmit and
receive functions) and has a predefined 20-bit pattern (that consists of a 10-bit control pattern and a 10-bit
skip pattern). The 10-bit skip pattern must be chosen from a code group with neutral disparity.
The rate match FIFO operates by looking for the 10-bit control pattern, followed by the 10-bit skip pattern
in the data, after the word aligner has restored the word boundary. After finding the pattern, the rate match
FIFO performs the following operations to ensure the FIFO does not underflow or overflow:
• Inserts the 10-bit skip pattern when the local receiver reference clock frequency is greater than the
upstream transmitter reference clock frequency
• Deletes the 10-bit skip pattern when the local receiver reference clock frequency is less than the upstream
transmitter reference clock frequency
The rate match FIFO supports operations in single-width mode. The 20-bit pattern can be user-defined for
custom configurations. For protocol configurations, the rate match FIFO is automatically configured to
support a clock rate compensation function as required by the following specifications:
• The PCIe protocol per clock tolerance compensation requirement, as specified in the PCI Express Base
Specification 2.0 for Gen1 and Gen2 signaling rates
• The Gbps Ethernet (GbE) protocol per clock rate compensation requirement using an idle ordered set,
as specified in Clause 36 of the IEEE 802.3 specification
In asynchronous systems, use independent reference clocks to clock the upstream transmitter and local
receiver. Frequency differences in the order of a few hundred ppm can corrupt the data when latching from
the recovered clock domain (the same clock domain as the upstream transmitter reference clock) to the local
receiver reference clock domain.
The rate match FIFO deletes SKP symbols or ordered sets when the upstream transmitter reference clock
frequency is higher than the local receiver reference clock frequency and inserts SKP symbols or ordered
sets when the local receiver reference clock frequency is higher than the upstream transmitter reference
clock frequency.
Related Information
• Transceiver Custom Configurations in Cyclone V Devices
• Transceiver Protocol Configurations in Cyclone V Devices
8B/10B Decoder
The receiver channel PCS datapath implements the 8B/10B decoder after the rate match FIFO. In configu-
rations with the rate match FIFO enabled, the 8B/10B decoder receives data from the rate match FIFO. In
configurations with the rate match FIFO disabled, the 8B/10B decoder receives data from the word aligner.
The 8B/10B decoder supports operation in single- and double-width modes.
Transceiver Architecture in Cyclone V Devices
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8B/10B Decoder
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