I 2 C Controller Block Diagram And System Integration - Altera Cyclone V Device Handbook

2
20-2
I C Controller Block Diagram and System Integration
• Transmit and receive buffers †
• Handles bit and byte waiting at all bus speeds †
• DMA handshaking interface †
2
I C Controller Block Diagram and System Integration
2
The I C controller consists of a slave interface, an I
two interfaces. †
The host processor accesses data, control, and status information about the I
slave interface.
Figure 20-1: I2C Controller Block Diagram
2
The I C controller consists of the following modules and interfaces:
• Slave interface for control and status register (CSR) accesses and DMA transfers, allowing a master to
access the CSRs and the DMA to read or write data directly.
• Two FIFO buffers for transmit and receive data, which hold the Rx FIFO and Tx FIFO buffer register
banks and controllers, along with their status levels. †
• Shift logic for parallel-to-serial and serial-to-parallel conversion
• Rx shift – Receives data into the design and extracts it in byte format. †
• Tx shift – Presents data supplied by CPU for transfer on the I
• Control logic responsible for implementing the I
Altera Corporation
I 2 C Controller
RX and RX FIFO
2
I C Interface
(to I/O Pins)
TX and RX Shift
RX Filter
Clock
Manager
Reset
Manager
L4 Peripheral Bus
2
C interface, and FIFO logic to buffer data between the
Interrupt Controller
Control
DMA Interface
Register Block
Slave Interface
2
C bus. †
2
C protocol.
2013.12.30
2
C controller through a 32-bit
MPU
IRQ
DMA
Controller
I2C Controller
Send Feedback
cv_54020