Gigabit Ethernet - Altera Cyclone V Device Handbook

CV-53004
2013.10.17
Table 4-2: Hard IP Configurations for PCIe Gen1 and Gen2
The following table lists the configurations allowed for each Cyclone V device when you use both PCIe Hard
IP blocks on the top and bottom transceiver banks. Support will vary by the number of transceiver channels
in a device.
Top PCIe Hard IP
x1
x2
x4
The following table lists the maximum number of data channels that can be enabled to ensure the
channels meet the PCIe Gen2 Transmit Jitter Specification. Follow this recommendation when
planning channel placement for PCIe Gen2 using Cyclone V GT or Cyclone V ST device variants.
Table 4-3: Recommended Channel Placement for PCIe Gen2
CMU channels are not counted as data channels.
5CGTD7F672, 5CGTD7F896, 5CGTD9F672,
5CSTD5F896, 5CSTD6F896
5CGTD9F896, 5CGTD9F1152
Related Information
Transceiver Architecture in Cyclone V Devices

Gigabit Ethernet

The IEEE 802.3 specification defines the 1000BASE-X PHY as an intermediate, or transition layer that
interfaces various physical media with the MAC in a gigabit ethernet (GbE) system, shielding the MAC layer
from the specific nature of the underlying medium. The 1000BASE-X PHY is divided into the PCS, PMA,
and PMD sublayers.
The PCS sublayer interfaces with the MAC through the gigabit media independent interface (GMII). The
1000BASE-X PHY defines a physical interface data rate of 1 Gbps and 2.5 Gbps.
Transceiver Protocol Configurations in Cyclone V Devices
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Bottom PCIe 5CGXC4,
Hard IP 5CGXC5,
5CGTD5, 5CSXC5,
5CSTD5
x1
x2
x4
x1
x2
x4
x1
x2
x4
Device
5CGXC7,
5CGTD7, 5CSXC6,
5CSTD6
Yes Yes
No Yes
No Yes
No No
No No
No No
No No
No No
No No
Maximum Channels Utilization
Gigabit Ethernet
5CGXC9, 5CGTD9
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
6
8
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