Interconnect; Features Of The Interconnect - Altera Cyclone V Device Handbook

2013.12.30
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The hard processor system (HPS) level 3 (L3) interconnect and level 4 (L4) peripheral buses are implemented
®
with the ARM
high-performance HPS interconnect based on the ARM Advanced Microcontroller Bus Architecture (AMBA
Advanced eXtensible Interface (AXI
™
Bus (APB ) protocols. The L3 interconnect implements a multilayer, nonblocking architecture that supports
multiple simultaneous transactions between masters and slaves, including the Cortex
unit (MPU) subsystem. The interconnect provides five independent L4 buses to access control and status
registers (CSRs) of peripherals, managers, and memory controllers
Related Information
infocenter.arm.com
Additional information is available in the AMBA Network Interconnect (NIC-301) Technical Reference
Manual, which you can download from the ARM website (infocenter.arm.com).

Features of the Interconnect

The L3 interconnect has the following characteristics:
• Main internal data width of 64 bits
• Programmable master priority with single-cycle arbitration
• Full pipelining to prevent master stalls
• Programmable control for FIFO buffer transaction release
• Security of the following types:
• Secure
• Nonsecure
• Per transaction security
• Five independent L4 buses
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™
CoreLink Network Interconnect (NIC-301). The NIC-301 provides a foundation for a
™
), Advanced High-Performance Bus (AHB

Interconnect

™
), and Advanced Peripheral
™
-A9 microprocessor
9001:2008
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