Emac Block Diagram And System Integration; Emac To Rgmii Interface - Altera Cyclone V Device Handbook

cv_54017
2013.12.30

EMAC Block Diagram and System Integration

Figure 17-1: EMAC System Integration
EMAC integration from a high level point of view.
The EMACs are integrated into the HPS portion of the system on a chip (SoC) FPGA device. They
communicate with the I/O pins.

EMAC to RGMII Interface

Table 17-1: External PHY Datapath In/Out Interface
EMAC Port
clk_tx_i
phy_txd_o
Ethernet Media Access Controller
Send Feedback
FPGA Fabric
PHY Transceiver
PHY
HPS
RGMII
PHY
MDIO/
I 2 C
Legend
TMSTP = Timestamp
In/Out
In
Out
EMAC Block Diagram and System Integration
2
GMII/MII/MDIO
TMSTP
PHY
EMAC0
MDIO
Pin
Multiplexer
EMAC1
I 2 C
(For Ethernet)
Width
1 Transmit Clock. This signal provides the
transmit clock for RGMII (125/25/2.5 MHz in
1G/100M/10Mbps). All PHY transmit signals
generated by the EMAC are synchronous to
this clock.
8 PHY Transmit Data. This is a group of eight
transmit data signals driven by the MAC.
Unused bits in the RGMII interface configura-
tion are tied to low. RGMII: Bits [3:0] provide
the RGMII transmit data. The data bus changes
with both rising and falling edges of the
transmit clock (clk_tx_i). The validity of the
data is qualified with phy_txen_o. Synchronous
to: clk_tx_i, clk_tx_180_i
AXI
DMA
CSR
L3
APB
Interconnect
Description
Altera Corporation
17-3