Altera Cyclone V Device Handbook page 855

17-6
EMAC to FPGA PHY Interface
Signal Name
phy_txer_o
rst_clk_tx_n_o
phy_clk_rx_i
phy_rxd_i
Altera Corporation
In/Out Width
Out 1
Out 1
In 1
In 8
Description
PHY Transmit Error: This signal is driven by
the MAC and has multiple functions depending
on which PHY interface is selected, as explained
below:
• GMII / MII: When high, indicates a transmit
error or carrier extension on the phy_txd
bus. Also used for signaling of low power
states in Energy Efficient Ethernet operation.
Synchronous to: phy_clk_tx_o.
• RGMII: Not used. Tied low in some
configurations; driven low in others.
Transmit clock reset output to the FPGA fabric:
This is the internal synchronized reset to
clk_tx_int output from the EMAC. May be used
by logic implemented in the FPGA fabric as
desired.
Receive clock from external PHY.
For RGMII, the clock frequency is 125/25/2.5
MHz in 1 G, 100 M, and 10 Mbps modes.
For GMII, the clock frequency is 125 MHz.
PHY Receive Data: This is a bundle of eight
data signals received from the PHY. It has
multiple functions depending on which PHY
interface is selected, as listed below:
• GMII: All 8 bits provide the GMII receive
data byte. The validity of the data is qualified
with phy_rxdv_i and phy_rxer_i. For lower
speed MII operation, only the bottom 4 bits
are used. Synchronous to: phy_ clk_rx_i.
• RGMII: Bits [3:0] provide the RGMII receive
data. The data bus is sampled on both rising
and falling edges of the receive clock
(phy_clk_rx_i). The validity of the data is
qualified with phy_rxdv_i. Synchronous to:
phy_ clk_rx_i (both rising and falling edges)
.
Ethernet Media Access Controller
cv_54017
2013.12.30
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