Altera Cyclone V Device Handbook page 294

CV-53001
2013.05.06
Figure 1-6: SX Device with Six Transceiver Channels and One or Two PCIe HIP Blocks
The PCIe HIP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 4 and Ch 5 of bank GXB_L1.
Usage Restrictions on Specific Channels
Channels next to PCIe Hard IP block are not timing-optimized for the 6.144 Gbps CPRI data rate. Avoid
placing the 6.144 Gbps CPRI channels in affected channels. The affected channels can still be used as a CMU
to clock the CPRI channels.
Table 1-1: Usage Restrictions on Specific Channels Across Device Variants
Channels
Ch 1, Ch 2
Ch 4, Ch 5
Ch 1, Ch 2
Cyclone V GX transceiver channels are comprised of a transmitter and receiver that can operate individually
and simultaneously—providing a full-duplex physical layer implementation for high-speed serial interfacing.
(1)
Impacted only if the device has PCIe HIP block located next to this bank.
Transceiver Architecture in Cyclone V Devices
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(2)
6 Ch
GXB_L1
GXB_L0
Transceiver
Bank Names
Notes:
1. 6 transceiver channels with one PCIe HIP block.
2. 6 transceiver channels with two PCIe HIP blocks.
Channel Bank Location
GXB_L0
(1)
GXB_L1
(1)
GXB_L2
Usage Restrictions on Specific Channels
Ch 5
PCIe Hard IP
Ch 4
6 Ch (1)
Ch 3
Ch 2
PCIe Hard IP
Ch 1
Ch 0
• No 6.144 Gbps CPRI support
• No support for PCS with phase compensation FIFO
in registered mode
Usage Restriction
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