Interrupts - Altera Cyclone V Device Handbook

12-12

Interrupts

Interrupts
All interrupt sources are combined to create a single level-sensitive, active-high interrupt (qspi_intr_in).
Software can determine the source of the interrupt by reading the interrupt status register (irqstat). By
default, the interrupt source is cleared when software writes the interrupt status register. The interrupts are
individually maskable through the interrupt mask register (irqmask). Table 12–2 lists the interrupt sources
in the irqstat register.
Table 12-3: Interrupt Sources in the irqstat Register
Interrupt Source
Underflow detected
Indirect operation complete
Indirect read reject
Protected area write attempt
Illegal data slave access detected
Transfer watermark reached
Receive overflow
TX FIFO not full
TX FIFO full
Altera Corporation
Description
When 0, no underflow has been detected. When 1,
the data slave write data is being supplied too slowly.
This situation can occur when data slave write data is
being supplied too slowly to keep up with the
requested write operation This bit is reset only by a
system reset and cleared to zero only when the register
is written to.
The controller has completed a triggered indirect
operation.
An indirect operation was requested but could not be
accepted because two indirect operations are already
in the queue.
A write to a protected area was attempted and rejected.
An illegal data slave access has been detected. Data
slave wrapping bursts and the use of split and retry
accesses can cause this interrupt. It is usually an
indicator that soft masters in the FPGA fabric are
attempting to access the HPS in an unsupported way.
The indirect transfer watermark level has been
reached.
This condition occurs only in legacy SPI mode. When
0, no overflow has been detected. When 1, an over
flow to the RX FIFO buffer has occurred. This bit is
reset only by a system reset and cleared to zero only
when this register is written to. If a new write to the
RX FIFO buffer occurs at the same time as a register
is read, this flag remains set to 1.
This condition occurs only in legacy SPI mode. When
0, the TX FIFO buffer is full. When 1, the TX FIFO
buffer is not full.
This condition occurs only in legacy SPI mode. When
0, the TX FIFO buffer is not full. When 1, the TX FIFO
buffer is full.
cv_54012
2013.12.30
Quad SPI Flash Controller
Send Feedback