Functional Description Of The Emac; Host Interfaces - Altera Cyclone V Device Handbook

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Functional Description of the EMAC

Figure 17-2: EMAC High-Level Block Diagram with Interfaces

There are two host interfaces to the MAC. The management host interface, a 32-bit slave interface, provides

access to the CSR set. The data interface is a 32-bit interface. It controls data transfer between the direct

memory access (DMA) controller channels and the rest of the HPS system through the NIC 301 L3

interconnect.

There is a built-in DMA controller which is optimized for data transfer between the MAC controller and

system memory. The DMA controller has independent transmit and receive engines, and a CSR set. The

transmit engine transfers data from system memory to the device port, while the receive engine transfers

data from the device port to the system memory. The controller uses descriptors to efficiently move data

from source to destination with minimal host intervention.

The EMAC also contains FIFO buffer memory to buffer and regulate the Ethernet frames between the

application system memory and the EMAC controller. On transmit, the Ethernet frames read into the

transmit FIFO buffer (1024 x 42 bits), and eventually trigger the MAC to perform the transfer. Received

Ethernet frames are stored in the receive FIFO buffer, also indicating the FIFO buffer bits fill level to the

DMA controller. The DMA controller then initiates the configured burst transfers. Both receive and transmit

transfer status are taken from the MAC and transferred to the DMA.

There are two host interfaces in the EMAC: a slave and a master. The master is connected to the L3 master

peripheral switch interface in the L3 interconnect block.

The EMAC CSR set access is provided by a slave interface. The slave is connected to the level 4 (L4) bus.

Ethernet Media Access Controller

Send Feedback

TX FIFO Buffer

TX FIFO Buffer

Operation Mode

Functional Description of the EMAC

RX FIFO Buffer

RX FIFO Buffer

Altera Corporation

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