Functional Description Of The I C Controller; Feature Usage; Behavior - Altera Cyclone V Device Handbook

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2013.12.30
• DMA interface that generates handshaking signals to the DMA controller in order to automate the data
transfer without CPU intervention. †
• Interrupt controller that generates raw interrupt and interrupt flags, allowing them to be set and cleared.
†
• Receive filter for detecting events, such as start and stop conditions, in the bus; for example, start, stop
and arbitration lost. †
Functional Description of the I

Feature Usage

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The I C controller can operate in standard mode (with data rates 0 to 100 Kbps) or fast mode (with data
rates less than or equal to 400 Kbps). Additionally, fast mode devices are downward compatible. For instance,
fast mode devices can communicate with standard mode devices in 0 to 100 Kbps I
standard mode devices are not upward compatible and should not be incorporated in a fast-mode I
system as they cannot follow the higher transfer rate and therefore unpredictable states would occur. †
You can attach any I
information back and forth. There needs to be at least one master (such as a microcontroller or DSP) on the
bus and there can be multiple masters, which require them to arbitrate for ownership. Multiple masters and
arbitration are explained later in this chapter. †

Behavior

You can control the I
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• An I C master only, communicating with other I
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• An I C slave only, communicating with one or more I
The master is responsible for generating the clock and controlling the transfer of data. The slave is responsible
for either transmitting or receiving data to/from the master. The acknowledgement of data is sent by the
device that is receiving data, which can be either a master or a slave. As mentioned previously, the I
protocol also allows multiple masters to reside on the I
bus ownership. †
Each slave has a unique address that is determined by the system designer. When a master wants to
communicate with a slave, the master transmits a START/RESTART condition that is then followed by the
slave's address and a control bit (R/W) to determine if the master wants to transmit data or receive data
from the slave. The slave then sends an acknowledge (ACK) pulse after the address. †
If the master (master-transmitter) is writing to the slave (slave-receiver), the receiver receives one byte of
data. This transaction continues until the master terminates the transmission with a STOP condition. If the
master is reading from a slave (master-receiver), the slave transmits (slave-transmitter) a byte of data to the
master, and the master then acknowledges the transaction with an ACK pulse. This transaction continues
until the master terminates the transmission by not acknowledging (NACK) the transaction after the last
byte is received, and then the master issues a STOP condition or addresses another slave after issuing a
RESTART condition. †
I2C Controller
Send Feedback
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C Controller
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C controller to an I C-bus and every device can talk with any master, passing
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C controller via software to be in either mode:
Functional Description of the I
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C slaves.
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C masters.
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C bus and uses an arbitration procedure to determine
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20-3
C Controller
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C bus system. However,
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C bus
2
C
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