Altera Cyclone V Device Handbook page 400

4-18
Transceiver Datapath in a XAUI Configuration
Figure 4-18: XAUI Configuration Datapath
Altera Corporation
Transceiver PHY IP
Lane Data Rate
Number of Bonded Channels
PCS-PMA Interface Width
Word Aligner (Pattern Length) (1)
8B/10B Encoder/Decoder (1)
Deskew FIFO (1)
Rate Match FIFO (1)
(1)
Byte SERDES
Byte Ordering (1)
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency
Note:
1. Implemented in soft logic.
XAUI PHY IP
3.125 Gbps
×4
10-Bit
10-Bit/K28.5
Enabled
Enabled
Enabled
Enabled
Disabled
16-Bit
156.25 MHz
Transceiver Protocol Configurations in Cyclone V Devices
CV-53004
2013.10.17
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