Document Revision History - Altera Cyclone V Device Handbook

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Document Revision History

Document Revision History
Date
January 2014
Altera Corporation
Version
2014.01.10 Removed Preliminary tags for clock resources, clock input pin
connections to GCLK and RCLK networks, and PLL features tables.
Updated clock resources table.
Updated GCLK, RCLK, and PCLK networks diagrams for Cyclone V E,
GX, and GT devices.
Added GCLK, RCLK, and PCLK networks diagrams for Cyclone V SE,
SX, and ST devices.
Added notes to dedicated clock input pin connectivity to GCLK and
RCLK tables for Cyclone V SE, ST, and SX devices.
Updated the following PLL locations diagrams:
Cyclone V GX C3 device
Cyclone V E A7 device, Cyclone V GX C7 device, and
Cyclone V GT D7 device
Added the following PLL locations diagrams:
Cyclone V SE A2 and A4 devices, and Cyclone V SX C2 and C4
devices
Cyclone V SE A5 and A6 devices, Cyclone V SX C5 and C6 devices,
and Cyclone V ST D5 and D6 devices
Added information on PLL migration guidelines.
Updated VCO post-scale counter,
Added information on PLL cascading.
Updated information on external clock output support.
Added information on programmable phase shift.
Updated automatic clock switchover mode requirement.
Changes
, to VCO post divider.
K
Clock Networks and PLLs in Cyclone V Devices
CV-52004
2014.01.10
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